Aldec Adds Ultra-Fast Code Coverage to RivieraRiviera Simulator Offers Built-in Mixed HDL Line Code Coverage that Accelerates HDL Debugging Process
Contact:
Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224
erics@aldec.com
Henderson Nevada, November 15th, 2001 - Aldec, Inc., a leading supplier of HDL design entry and verification tools for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today the release of Riviera with built-in Line Code Coverage for UNIX, Linux and Windows NT/2000/XP. The growing complexity of today's designs requires more time spent on design verification than on conceptual work. Riviera's built-in Line Code Coverage cuts design debug time and optimizes the HDL source code written in either VHDL, Verilog or mixed VHDL/Verilog languages.
Built-In Line Code Coverage
Riviera is a high-performance, mixed HDL simulation solution that includes the built-in Code Coverage product, which enables designers to optimize their VHDL, Verilog or mixed HDL source code without the overhead of connecting through PLI, FLI or VHPI interfaces. When performance counts, built-in code coverage is the key to obtaining the maximum performance with minimal operating system overhead.
Mixed VHDL and Verilog Coverage Features
Built-in Code Coverage checks for execution of all VHDL or Verilog statements during simulation and provides a detailed report indicating which parts were not covered by the testbench and which VHDL or Verilog statements were not executed. Coverage data can be collected either on a per-unit or per-instance basis. Sessions can also be controlled interactively with macros during simulation, allowing the design to turn the coverage on or off for specific regions of the design. Since Riviera's Line Code Coverage can be run in parallel with simulation, it provides on-line analysis of code efficiency and testing quality.
Integrated Code Coverage Viewer
All Code Coverage data can be viewed with the stand-alone Code Coverage Viewer. The viewer shows a synchronized display of the design structure and source code with coverage data. When a designer invokes and runs Code Coverage, the results are stored in a user-defined file. Using the Viewer, the designer can see all pertinent information of the design's processes and the data gathered can be presented in either a graphical or textual form. The result of coverage is measured as a percentage given by dividing the number of statements executed by the total number of executable statements in the instance.
"By offering built-in Code Coverage, Riviera improves design quality while eliminating the overhead normally associated with this process; Aldec is constantly committed to performance and quality improvements such as this to help designers work more productively and ultimately decrease time-to-market," stated Eric Seabrook, Riviera Product Marketing Manager for Aldec.
Price And Availability
Current Riviera customers will have the ability to add Code Coverage to their existing Riviera simulator for $3,500.00. Riviera includes an HDL editor, Waveform Viewer, Debugging tool and the choice of a VHDL, Verilog or mixed simulation kernel. The first year's maintenance is included in the initial sale price. Pricing for Riviera starts at $12,500. To receive more information about Riviera, please visit Aldec at www.aldec.com or call 702-990-4400
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
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Riviera and Incremental Prototyping Technology are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners
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